Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Explain VLSI Design flow using Y-chart.
7 M
1 (b) Explain the fabrication steps of nMOS transistor with necessary figures.
7 M

2 (a) Draw the CMOS Inverter circuit and VTC for different operation regions of the nMOS and pMOS transistor. Derive critical voltage points VOH, VOL, VIL and VIH.
7 M
Answer any two question from Q2 (b) or Q2 (c)
2 (b) An enhancement nMOS transistor has the following parameters: Threshold voltage Vth=0.8v, channel length modulation coefficient λ=0.05V-1, Process transconductance parameter μn Cox = 20A/V2. If the transistor is biased with VG=2.8V, VD=5V and VS=1V. The drain current is say ID=0.24mA. Determine W/L.
7 M
2 (c) Design a CMOS logic gate for the function f= ab+ac+bd using smallest number of transistors.
7 M

Answer any two question from Q3 (a), (b) or Q3 (c), (d)
3 (a) Explain energy band diagram of MOS structure at surface inversion and derive the equation of threshold voltage.
7 M
3 (b) Derive the expression for drain current as a function of V GS , V DS and V SB for all three region of operation of MOSFET using Gradual Channel Approximation.
7 M
3 (c) How will you calculate propagation delay times τpHL and τpLH for CMOS Inverter?
7 M
3 (d) Explain Voltage Bootstrapping.
7 M

Answer any two question from Q4 (a), (b) or Q4 (c), (d)
4 (a) Explain the functioning of depletion load nMOS inverter and derive critical voltage points VOH, VOL, VIL and VIH.
7 M
4 (b) Explain two input depletion load NOR gate and derive the necessary equations for the same.
7 M
4 (c) Explain the basic principle of pass transistor circuit. Explain logic "1" transfer and logic "0" transfer.
7 M
4 (d) Draw the circuit diagram of Domino CMOS logic gate and discuss it in detail.
7 M

Answer any two question from Q5 (a), (b) or Q5 (c), (d)
5 (a) Discuss basic steps of the LOCOS Process.
7 M
5 (b) Concept of regularity, modularity and locality.
7 M
5 (c) Write a short note on Built In Self Test (BIST).
7 M
5 (d) Give comparison between FPGA and CPLD.
7 M



More question papers from Vlsi Technologies
SPONSORED ADVERTISEMENTS