STUPIDSID
Answer any one question from Q1 and Q2
1 (a) (i)
Subtract (27.50)10 from (68.75)10 using 2's complement method.
4 M
1 (a) (ii)
Explain the TTL characteristics-speed of operation and Fan-out.
2 M
1 (b)
Design Full adder using 4:1 multiplexer.
6 M
2 (a)
Convert the following numbers, show all the steps:
i) (101101.10101)2=( )10
ii) (247)10 = ( )8
iii) (0.BF85)16=( )8
i) (101101.10101)2=( )10
ii) (247)10 = ( )8
iii) (0.BF85)16=( )8
6 M
2 (b)
Compare TTL and CMOS logic family. Draw CMOS NOR gate.
6 M
Answer any one question from Q3 and Q4
3 (a)
Design JK flip-flop using SR flip-flop.
6 M
3 (b)
Design sequence detector to detect the sequence ----1011---- using JK-flip-flop.
7 M
4 (a)
Design and draw logic diagram of Mod-82 counter using IC7490.
6 M
4 (b)
Draw the ASM chart of washing machine with the following
Conditions:
(i) Start the machine
(ii) Drain the previous existing water
(iii) Choose HOT or COLD water option
(iv) Pump in fresh water to fill washer tub
(v) Complete Washing cycle
(vi) Complete Rinsing cycle
(vii) Complete Drying cycle.
Assume the following inputs:
(1) H/C 1 = HOT, 0 = COLD
(2) Start 1 = Start, 0 = Stop
(3) Empty 1 = Washer tub completely empty 0 = Washer tub is full
(4) Time 1=Time is over 0 = Time is not over.
(i) Start the machine
(ii) Drain the previous existing water
(iii) Choose HOT or COLD water option
(iv) Pump in fresh water to fill washer tub
(v) Complete Washing cycle
(vi) Complete Rinsing cycle
(vii) Complete Drying cycle.
Assume the following inputs:
(1) H/C 1 = HOT, 0 = COLD
(2) Start 1 = Start, 0 = Stop
(3) Empty 1 = Washer tub completely empty 0 = Washer tub is full
(4) Time 1=Time is over 0 = Time is not over.
7 M
Answer any one question from Q5 and Q6
5 (a)
Design full subtractor using PLA.
6 M
5 (b)
Explain difference between PAL and PLA.
6 M
6 (a)
Draw and explain the structural block diagram of FPGA.
6 M
6 (b)
Explain the difference between CPLDs and FPGAs.
6 M
Answer any one question from Q7 and Q8
7 (a)
What is VHDL ? Write features of VHDL. Explain the structure of VHDL module.
6 M
7 (b)
Explain the following three data objects variables, constants and signals used in VHDL code with respect to need, location of declaration in VHDL module, syntax and example.
6 M
8 (a)
Explain the difference between concurrent and sequential statements with example.
6 M
8 (b)
Write entity, architecture and package declaration for 3 bit synchronous up/down counter with asynchronous clear input.
7 M
More question papers from Digital Electronics & Logic Design